1. Field of the Invention
The present invention relates to a delay time control circuit for applying a delay time to input signals. More particularly, the present invention relates to a delay time control circuit, which permits the regulation of the delay time.
2. Description of the Related Art
Recently, high speed and precise operation of a semiconductor device has, in general, become well advanced. Therefore, a tester, etc. for measuring the characteristics of the semiconductor device is required to provide accurate measurement of devices with high speed operation. To realize the measurement accuracy for devices with high speed operation, out-phasing of output timing in output signals from the devices employed in the internal circuits of the tester needs to be eliminated. Therefore, as one means to solve the foregoing problem, a delay time control circuit is employed to permit the regulation of the delay time.
A conventional delay time control circuit is illustrated in FIGS. 1 and 2. A decoder 1 outputs eight bits from the associated terminals B0 through B7 in response to an externally transmitted control signal. Each of the eight bits, B0 through B7, are coupled to each of the first input terminals of AND gates 2a through 2h, respectively. In response to the control signal, the decoder 1 outputs a "1" state signal (i.e., high level signal, hereinafter referred to as H level signal) from any one of the associated terminals B0 through B7 of the digital signal, and a "0" state signal (i.e., low level signal, hereinafter referred to as L level signal) from the other remaining seven terminals. An input signal SGin is coupled to an input of OR gate 3a. An output signal from the OR gate 3a is coupled to a second input terminal of the AND gate 2a and an input of OR gate 3b.
An output signal from the OR gate 3b is coupled to a second input terminal of the AND gate 2b and an input of OR gate 3c. An output signal from the OR gate 3c is coupled to a second input terminal of the AND gate 2c and an input of OR gate 3d. An output signal from the OR gate 3d is coupled to a second input terminal of the AND gate 2d and an input of OR gate 3e. An output signal from the OR gate 3e is coupled to a second input terminal of the AND gate 2e and an input of OR gate 3f. An output signal from the OR gate 3f is coupled to a second input terminal of the AND gate 2f and an input of OR gate 3g. An output signal from the OR gate 3g is coupled to a second input terminal of the AND gate 2g and an input of OR gate 3h. An output signal from the OR gate 3h is coupled to a second input terminal of the AND gate 2h. Output signals from the AND gates 2a through 2h are coupled, respectively, to an 8-input OR gate 4, so that the 8-input OR gate 4 outputs an output signal SGout.
As an example, in the delay time control circuit having the above-described circuit configuration, when the input signal SGin is input to the OR gate 3a while only one bit, B0, is in the H level, the input signal SGin is transmitted through the OR gate 3a, the AND gate 2a, and the 8-input OR gate 4 as the output signal SGout. Further, when the input signal SGin is input with only one bit, B2, in the H level, the input signal SGin is transmitted as the output signal SGout, through the OR gates 3a, 3b and 3c, the AND gate 2c, and the 8-input OR gate 4. Therefore, since the number of stages of the OR gates 3a through 3h through which the input signal SGin passes can be controlled, the delay time of the output signal SGout with respect to the corresponding input signal SGin can be selected, depending on which one bit of the digital signal is in the H level.
One example of a cell layout on a semiconductor substrate for the delay time control circuit is shown in FIG. 2. A first cell array 5 comprises the OR gates 3a through 3h and the AND gates 2a through 2h. A second cell array 6 includes the 8-input OR gate 4 and the decoder 1. The input signal SGin is coupled to an input terminal Ti of the OR gate 3a. Output terminals To of the OR gates 3a through 3g are connected to input terminals Ti of the OR gates 3b through 3h disposed at the successive stage and first input terminals Ti of the AND gates 2a through 2g, by conducting lines La through Lg, respectively.
The output terminal To of the OR gate 3h is connected to the first input terminal Ti of the AND gate 2h by the conducting line Lh. The second input terminals Ti of the AND gates 2a through 2h are connected to outputs B0-B7 of the decoder 1, respectively, by conducting lines Li. The output terminals To of the AND gates 2a through 2h are connected, respectively, to the input terminals of the 8-input OR gate 4, by conducting lines Lo.
In this configuration, in order to accurately regulate the delay time of output signal SGout according to the digital signal output by the decoder 1 at the terminals B0 through B7 and then propagated through respective AND gates 2a through 2h, the delay time for a single stage of the OR gates 3a through 3h should be regulated and matched to one another.
However, the output signal from each of the OR gates 3a through 3g is coupled from its single output terminal To to each of the AND gates 2a through 2g and to each of the OR gates 3b through 3h disposed at the successive stage by conducting lines, La through Lg, which are branched away at their midpoints. The output signal from the OR gate 3h is coupled only to AND gate 2h by a conducting line Lh, which is not branched away. Therefore, the length of the conducting line connected to the OR gate 3h differs from those for the OR gates 3a through 3g, with the lengths of the conducting lines connected to the output terminals of the OR gates 3a through 3g being greater. Therefore, the design of the circuit layout becomes considerably difficult in order to align the delay times. For example, in the first cell array 5 as shown in FIG. 2, the lengths of the conducting lines La through Lh are inventively arranged to be equal in length by mingling the AND gates 2a through 2h with the OR gates 3a through 3h, respectively, in order to align the delay time caused by the respective conducting lines of the OR gates 3a through 3h.
As a result, the lengths of the conducting lines La through Lh are equalized to the longest length. Therefore, as the lengths of the conducting lines are increased, capacitance of the conducting lines is increased, resulting in jitter generated in the output signals.
Further, as the lengths of the conducting lines La through Lh are increased, the number of the conducting lines disposed between each one of the cell arrays 5 and 6 is increased. Therefore, when the cell layout in the bulk stage is altered during the manufacturing of a cell array, for example, spacing between adjacent conducting lines will be reduced, because the area shared for conducting lines is kept fixed. Cross-talk can then occur between the closely disposed conducting lines.
On the other hand, an input signal SGin is transmitted as a respective output signal SGout by propagation through at least one stage of the OR gates 3a through 3h, the corresponding stage of the AND gates 2a through 2h, and the 8-input OR gate 4. Therefore, a shorter delay time than that caused by the above-described three stages cannot be selected, and a delay time control circuit to accurately calibrate the delay time cannot be designed.
As the number of elements for the circuit of the 8-input OR gate 4 disposed at the last stage increases, the operation speed is substantially reduced. In order to equalize the lengths of the conducting lines, the lengths of the conducting lines connecting the AND gates 2a through 2h and the 8-input OR gate 4 is standardized to the longest length thereof. Therefore, a high frequency input signal SGin cannot be efficiently followed, and characterization of a high frequency signal is rather inadequate.